Problem Description:
Some Arm CPUs have errata where the ordering of stores and the
TLBI+DSB sequence may be incorrect. If one CPU stores to a virtual
address while another CPU invalidates the translation for that
address, the second CPU's TLBI+DSB may complete before the first
CPU's store has been globally observed.
Impact:
This erratum may allow software to write to a previously writable
location after the page table is modified to forbid writes to that
location. Consequently this may allow software to write to memory
owned by a higher exception level, possibly allowing software to
escalate privilege to that higher exception level.